Metal-oxide-semiconductor (MOS) devices are basic building elements in integrated circuits. In conventional MOS devices, gate electrodes often include polysilicon doped with p-type or n-type impurities, using doping operations such as ion implantation.
MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, also referred to as a poly depletion effect (also known as polysilicon depletion). The poly depletion effect occurs when an applied electric field sweeps away carriers from a region of a gate electrode close to a gate dielectric, forming a depletion layer. In n-doped polysilicon, the depletion layer includes ionized non-mobile donor sites. Whereas, in p-doped polysilicon, the depletion layer includes ionized non-mobile acceptor sites. The depletion effect increases the effective gate dielectric thickness, making it more difficult for an inversion layer to be created at the surface of the semiconductor.
To reduce the poly depletion effect, a metal layer may be inserted between a polysilicon gate electrode and the underlying gate dielectric. FIG. 1 illustrates a conventional MOS device having an inserted metal layer. The MOS device includes a gate stack including gate dielectric 4, inserted metal layer 6 over gate dielectric 4, and polysilicon gate electrode 8 over the inserted metal layer 6. In a typical process for forming the gate stack, a gate dielectric layer, a metal layer, and a gate electrode layer are blanket formed and patterned. The polysilicon gate electrode layer is implanted (pre-doped) with an impurity of a desired conductivity type. Then the stacked layers are patterned to form the gate stack. To avoid the implant-induced damage to gate dielectric 4, the energy and dosage of the implanted impurity are limited. As a result, lower portion 10 of polysilicon gate electrode 8 has a low impurity concentration. This has two adverse effects. First, the resistivity in lower portion 10 is high. When a voltage is applied on polysilicon gate electrode 8, a voltage drop may occur in lower portion 10 (partially due to a possible gate leakage current), and the effective gate voltage Vg applied on gate dielectric 4 is reduced. Consequently, the device drive current is reduced. Second, for optimum performance, the work function of polysilicon gate electrode 8 needs to be adjusted to the corresponding band-edge work function, which depends on the conductivity type of the corresponding MOS device. The work function of polysilicon gate electrode 8 may be adjusted through implanting appropriate impurities. However, since the energy and dosage of the pre-doping are limited, it is hard to adjust the work function to corresponding band-edges. A solution is thus needed to solve the above-discussed problems.